South Korean radar technology startup bitssensing has launched its new mini healthcare radar mini-H, the smallest high-resolution 60GHz IoT radar sensor in its series. The innovation behind the mini-H showcases the company’s industry-leading expertise in designing and manufacturing cutting-edge radar technologies that can transform healthcare, automotive, mobility, smart home, security, and more.

Dr. Jae-Eun Lee, CEO of Bitensing, a seasoned engineer in radar technology and formerly part of Mando Corp.’s Automotive World, knows what it takes to create a safe and convenient connected world. “Revolutionary technologies like mini-H are powering every aspect of our daily lives,” Lee said. “We are committed to integrating these breakthrough radar technologies to help build smart lives and smart cities, ultimately improving Quality of life for all.”

The advanced mini-H sensor is fixed to the wall and can detect the presence, movement, breathing or absence in real time and drop by measuring breathing patterns and pulsating blood vessels without the use of invasive cameras or wearable devices.

Designed for smarter and safer remote medical monitoring systems, the mini-H can be used in dark or wet locations and works regardless of clothing or blankets. Bluetooth and WiFi communication modules allow for seamless transfer of data from the radar to the dashboard or app for easy tracking. This completely wireless product allows for quick and easy software improvements, ensuring the product is always up to date. The product’s sleek, compact aesthetic also makes it easy to integrate, while the plug-and-play style provides instant monitoring of activity with the option to adjust settings for optimal personalization.

As a leading radar solutions company, bitsensing provides a complete end-to-end service, creating customizable radars (such as mini-H) with convenience and safety that exceed industry standards. The flexible bit-sensing architecture enables the team to quickly deliver robust products while working directly with end customers in a wide variety of industries to? ? Ensure satisfaction and broaden their horizons of what is possible in a smart life.

CES attendees can visit bitsensen’s virtual booth from January 11-14, 2021 to learn more about the mini-H. To view the mini-H informational product video, please visit here. If you are interested in learning more about our radar solutions, please visit www.bitsensing.com.

mini-H Product Specifications

Specifications are subject to change without notice. All features, functions, specifications and other product information provided in this document, including but not limited to product benefits, design, price, components, performance, availability and functionality, are subject to change without notice.

*Data driven by respiration detection may be limited and is designed for apnea detection

** Weight without cables

【Introduction】In nanotechnology for automotive SoCs, most defects on silicon are due to timing problems. Therefore, full-speed coverage requirements in automotive design are very stringent. In order to meet these requirements, engineers put a lot of effort into obtaining higher real-speed coverage. The main challenge is to obtain silicon of the required quality in high yields at the lowest possible cost. In this article, we discuss issues related to overtesting and undertesting in real-time test that can lead to yield problems. We will provide some suggestions to help overcome these problems.

In nanotechnology for automotive SoCs, most defects on silicon are due to timing issues. Therefore, full-speed coverage requirements in automotive design are very stringent. In order to meet these requirements, engineers put a lot of effort into obtaining higher real-speed coverage. The main challenge is to obtain silicon of the required quality in high yields at the lowest possible cost. In this article, we discuss issues related to overtesting and undertesting in real-time test that can lead to yield problems. We will provide some suggestions to help overcome these problems.

The main purpose of at-speed testing is to detect any timing failures that may occur in the silicon at its operating frequency. The important part to test is the logic that generates controllable clock pulses at the same frequency as required for functional operation. A method of providing controlled clock pulses is via an input pad slave tester (ATE), as this reduces complexity and minimizes the need for additional test logic to be built into the design.

However, this approach has frequency limitations because pads typically cannot support very high frequency clocks. Therefore, an on-chip phase-locked loop (PLL) and oscillator are used to provide the clock pulses. However, the free-running clocks of these cannot be used directly, because first we have to shift the vector through the scan chain at a low frequency (shift frequency), capture at the functional frequency, and then clear the data at the shift frequency. We need controllable pulses while capturing at the functional frequency, which can be achieved by using chopping logic. Figure 1 shows a typical clock architecture with full-speed clocks.

FIGURE 1: TYPICAL CLOCKING ARCHITECTURE WITH FULL SPEED CLOCKS

For any SoC, STA (Static Timing Analysis) signoff is integral to verifying timing performance. Timing signoff ensures that the silicon will run at the desired functional frequency. The same logic applies to full speed testing. STA signoff must be done for both full-speed and functional modes because the clock paths may be different in full-speed mode and the added test control logic also needs to be timed. The chopping logic is not required in normal functional mode, so we also need to meet the timing requirements for the chopping logic.

Ideally, it shouldn’t be a problem to turn off timing in full speed mode if the changes to the clocks are done in a common path, eg at the beginning of the clock path, so that the changes to the start and capture flip-flops are common and thus don’t Affects the setup and hold timing of the design. Test control logic generally works at low frequency or static, so it is not difficult to meet timing requirements.

Typical SoC Clocking Scheme

However, modern SoC design is not that simple. High performance and low leakage requirements lead to designs with various clock sources such as PLLs, oscillators, clock dividers, etc. in a single SoC. Depending on the architecture, there may be many IO interfaces running on an external clock of several MHz, such as SPI, JTAG, I2C, etc. Therefore, different parts of the SoC can run at different frequencies.

This is where things get complicated. The previously discussed clocking solution (chopping logic) for full-speed clocks is not sufficient for complex chips running at different frequencies. In full speed testing, these complexities lead to problems known as undertesting and overtesting, which lead to the need for testing.

Overtesting occurs when logic is tested at a higher frequency in full speed mode than it is running in functional mode. Referring to Figure 2, if pll_clock is provided to any low frequency modules like watchdog and RTC in full speed mode, overtesting will occur. A key reason for this approach is the simplicity of the test clock path, since this approach requires only changes to the functional logic. In our example we just need to bypass all divided clocks/RC osc clocks/external clocks by scan clock which in turn will be controlled by pll clock.

Figure 2: Memory and Flash run on the divided PLL clock, while the platform works on the actual pll_clock. The internal RC oscillator clocks blocks such as the RTC (Real Time Counter) and Watchdog Timer, which require very slow clock frequencies. Building blocks like the Display Master have both an IPS port and a camera port. The IPS interface typically operates at the system frequency, while the camera logic operates at an externally provided slower frequency clock. IO interfaces such as SPI and JTAG operate at a few MHz. Therefore, the overall configuration of the SOC requires multiple blocks operating at multiple frequencies.

Undertesting occurs when any logic is tested in full speed mode at a frequency lower than the expected operating frequency. This situation usually exists when it is not possible to provide a test clock at the same frequency as the functional mode, but at the same time it is not possible to shut down the design at a high frequency due to large data path delays or technical limitations. In this case, we are forced to provide a lower frequency clock.

Therefore, it is necessary to test the silicon for defects at exactly the same frequency as the functional frequency. Any deviation can lead to over-testing or under-testing problems:

• When the functional logic is designed to operate at a lower frequency, shutting down the higher frequency design for full speed testing will impact overall design area and power. In the case of timing critical designs, real-time test tools will use high drive strength cells and may even require low Vt cells to meet these frequency targets.

• Even if the design’s timing closes at a higher frequency, at the expense of power and area, we can be unnecessarily pessimistic in our yield calculations. Unrealistic yield drops can occur during at-speed testing. For example, in a design with two clock domains (domain1 @ 120MHz and domain2 @ 80MHz), we closed the timing of the entire design at 120MHz flat to simplify the clocking architecture in full speed mode. All ATPG pattern generation for both domains will occur at 120MHz. Due to process variability, on silicon, domain1 works fine at 120MHz, but domain2 only works at 110MHz, so all dies will be considered defective parts. Although the chip is functional enough, based on the failure of the full speed mode, we will declare the chip as a failed chip, which will reduce our yield.

• In the case of insufficient testing, the full speed mode cannot guarantee that the chip will actually work at the expected frequency. Since bad chips can pass the full-speed test, the purpose of the original full-speed test to filter out bad chips is defeated. In this case, we would be overly optimistic in our yield calculation.

With the shortcomings in mind, we will focus on the reasons for overtesting and undertesting in any SoC:

Simplicity of Clock Architecture

Given that there are so many clock sources in functional mode, it is easy to provide a small number of controllable test clocks in full speed mode.

Figure 3: A simple and simple test clock solution is to multiplex the PLL clock with an external clock, even for full-speed mode, which is a case of overtesting.

Let’s take the DSPI Module as an example. The IP operates on 2 clocks, a 15 MHz external clock and a 120MHz functional PLL clock for the internal logic. As shown in Figure 3, the simple and easy test clock solution is to multiplex the PLL clock with an external clock, even for full-speed mode, which is a case of overtesting.

Dividers in Nanodesign

For the clock divider, the original source clock is used for all test modes and multiplexed with the divided clock, as shown in Figure 4 below.

FIGURE 4: The original source clock is used for all test modes and multiplexed with the divided clock.

This is a common scenario in designs where we have many crossovers but we cannot use them in full speed testing because these crossovers are not controllable (phase determined) during the test. Therefore, an easy way to simplify testing at full speed is to provide an undivided clock in test mode, which leads to overtesting.

Timing exceptions such as multicycle paths

Various timing exceptions in the form of multicycle paths, false paths, profiling, etc. are used in designs when signal propagation requires more than a single-cycle clock during functional operation. These exceptions are valid in at-speed mode, so should also be properly migrated to full-speed mode in the form of SDC (Standard Design Constraints Document). However, current ATPG tools have limitations in understanding some of these constraints, especially multicycle paths. When parsing through an SDC file, it ignores multicycle paths and does not create any schema for them. For example, if we have a multicycle of 2 from one register to another, it will simply mask any patterns that check for captures between those two registers.

So this means that all multi-cycle paths are not tested at full speed, resulting in undertesting. On the other hand, if these exceptions are not part of the SDC file, the timing checks will happen in a single clock cycle, while functionally the path will work in two clock cycles, which is a typical case of overtesting. In general, this is a big problem, because usually we have many multi-cycle exceptions in any complex design, which can lead to over-testing or under-testing if we take the traditional approach.

real-time test

So far we’ve seen that neither overtesting nor undertesting is desirable, so we need a way to ensure that the real benefits of real-time testing are realized without compromising the QOR of the design. The idea is that there shouldn’t be any significant area/power overhead on the design due to real-time testing, but at the same time we should make sure that the real-time test design is checked at the expected functional frequency, not above or below that frequency.

Here is a list of some guidelines/techniques to ensure full speed testing is done the right way:

• Identify different frequency domains in your design in func mode. This is an important step because the sooner you determine the frequency domain, the better you can understand at-speed test requirements. A thorough analysis of the clocking architecture helps to define a defined full-speed clock. For example, when starting a project, there is usually not much emphasis on frequency targets for external IO interfaces, which can later affect defining a full-speed clocking strategy for these interfaces.

• Definition of full-speed mode timing constraints and generation of functional mode constraints. Any timing critical paths in full speed mode can be addressed at the beginning of the design cycle. It’s always easier to make changes at an early stage.

• One of the key solutions is to identify under-testing and over-testing situations, as many times these issues pop up during the final STA run and are not even noticed when timing is met. Using some kind of script, it is possible to compare the frequency of all registers in functional mode and full speed mode. Divide the registers into three categories: Flip-flops with the same frequency in both modes – can be used; Flip-flops in full-speed mode have a lower frequency than in functional mode – the case in the test; Flip-flops in full-speed mode Higher frequencies than in functional mode – a case of overtesting.

Once these cases are identified, a thorough analysis should be performed and all architectural possibilities explored to provide a clock at the exact same frequency as in functional mode.

To resolve timing anomalies, the solution is to convert multi-cycle paths to single-cycle paths by testing at a lower frequency. The concept is simple. Consider a design operating at 200MHz with several 2 multicycle paths. Timing these paths at 200MHz with a multicycle of 2 is equivalent to testing the paths at 100MHz in a single cycle. In full speed testing, the logic is tested in two passes. In a pass, a capture clock of 200MHz will be provided to test all single-cycle paths and all multi-cycle paths will be masked. In the second pass, a capture clock of 100MHz is provided to test all multicycle paths only. The same concept can be applied to higher multicycles.

Performing at-speed testing multiple times will also solve the problem of over-testing/under-testing to a large extent. As we discussed above, it is sometimes not possible to clock all domains at the same frequency, but we can do this by capturing clocks at multiple frequency configurations per pass. Usually, in our design where pll is used as system clock, we have the flexibility to configure pll to some discrete frequency.

Overtesting issues associated with crossovers can be resolved using the same multiple testing approach. The difference is that in case of multicycle paths flip-flops can be masked but in case of dividers we need controllability of the divided clock so that the clock can be gated in scan mode.

Figure 5: When the system clock is 200Mhz, during the at-speed test on channel 1, the clock gating logic will gate the clock to the domain that normally operates at 100Mhz (by dividing by 2 logic).

As shown in Figure 5, during the first run at full speed with the system clock at 200Mhz, the clock gating logic will gate the clock to the domain that normally runs at 100Mhz (by dividing by 2 logic). But in round 2, when the system clock is set to 100Mhz, the enable of the clock gating cell will be driven to logic 1. This will ensure that the logic is now tested at the expected frequency of 100Mhz.

Using the guidelines above, it should be possible to resolve most issues related to over- and under-testing. But in case forced to choose between undertesting and overtesting, the decision depends on the application of the SoC. In automotive design, where personal safety is the primary consideration, safe over-testing methods should be chosen, while in power-hungry designs, such as in networking and wireless, testing is required. Even for these cases, every effort should be made to ensure that the deviation from the desired frequency is as small as possible.

Let’s take an example of a design with multiple frequency clocks that will help understand the concept:

Assuming a design operating at 240MHz, we have a multicycle of 2, 3, 4, etc. for the various paths. There are also interfaces that operate on external clocks of 10MHz and 60MHz. To avoid any kind of over-testing or under-testing, run the test multiple times in full speed mode. Configure the PLL at 240, 120, 80, 60MHz and test all logic at actual functional speed.

• 1st pass: @240MHz – all single cycle paths (masked 100MHz and 60MHz interfaces, rest of SDC is normal)
• 2nd pass: @120MHz – path for multicycle 2 (removes multicycle 2 exception from SDC) + 100MHz interface logic (overtested)
• 3rd pass: @80MHz – path with multicycle 3 (removes all multicycle anomalies from 2 and 3)
• 4th pass: @60MHz – 4 paths + multicycle paths for 60mhz interface logic (remove all multicycle anomalies)

in conclusion

As SoC functionality becomes more complex and technology moves to lower nodes, good yield is proving to be an important concern for any design house. Yields directly impact the profit and loss equation, and serious effort is needed to address the causes of low yields. At-speed testing is an important measure of silicon quality, so we should aim for high coverage. But at the same time, we should only run our real-speed mode at the proper clock frequency, because testing at the wrong clock frequency can cause problems with overtesting or undertesting. These two situations (undertesting and overtesting) are not conducive to design QOR, nor to yield estimation.

Test clocks should be as important as functional clocks, and efforts should be made to provide clocks of the same frequency to different domains as they are clocked in functional domains. At the same time, considerable attention should be paid to multicycle paths, since they often form an important part of the timing paths in any design. At-speed testing in multiple pass is a method to solve multi-cycle path at-speed testing. The Multipass testing approach can also be used to address other over-testing and under-testing situations. So, in conclusion, using the above suggestions and methods, we can achieve more accurate full-rate coverage, which in turn will ensure that we minimize yield degradation issues without compromising the QOR of the design.

As we all know, one of the “highlights” of my country’s higher education in 2020 is the transfer of independent colleges. Among them, in addition to the independent colleges that can be successfully converted into new schools, there are still some schools that can only stop enrollment and stop running schools. So, what are the independent colleges that have stopped enrolling at the moment? Why did Bei Shizhu stop running the school?

1. List of independent colleges that have stopped enrolling students

In 2020, the Ministry of Education requires all independent colleges in the country to speed up the transfer process. Many of them have been converted into private or public colleges, but there are also a few colleges and universities that can only stop running schools for various reasons. There are at least five such independent colleges:

1. Beijing Normal University Zhuhai Branch

Location: Zhuhai, Guangdong

At present, Beijing Normal University Zhuhai Campus and Beijing Normal University Zhuhai Campus co-exist in one school. From 2019, the school began to gradually reduce the enrollment plan,Enrollment will stop in 2021, and the school will be terminated in July 2024and all merged into the Zhuhai Campus of Beijing Normal University.

2. Business School of Hebei University

Location: Baoding, Hebei

On January 26, 2021, the Ministry of Education issued the “Letter of the Ministry of Education on Approving the Business School of Hebei University to realize the transfer by terminating the school-running method”, announcing that it agreed to the business school of Hebei UniversityAdmissions will be suspended from 2020and realize the transfer by terminating running schools and gradually returning to running colleges and universities.

3. Jinling College of Nanjing University

Location: Nanjing, Jiangsu

Currently, the Suzhou campus of Nanjing University is under construction. On July 22, 2020, Jinling College of Nanjing University issued a letter to all alumni, indicating that the school willFrom September 2020, general undergraduate enrollment will be stopped, and it will be fully integrated into Nanjing University Suzhou Campus in 2022. At the same time, Jinling College alumni will receive the “Nanjing University Alumni Card” issued by the Alumni Association.

4. Hanlin College of Nanjing University of Traditional Chinese Medicine

Location: Taizhou, Jiangsu

Nanjing University of Traditional Chinese Medicine Hanlin College2020 Fall Enrollment Closed, while the Taizhou campus of Nanjing University of Traditional Chinese Medicine began to recruit students at the same time. In addition, the former campus will be set up as the Taizhou campus of Nanjing University of Traditional Chinese Medicine, and after the students complete their studies, Nanjing University of Traditional Chinese Medicine will take back the right to run the school and be responsible for the disposal of the South Hanlin College of Traditional Chinese Medicine.

5. School of Science and Technology, Xinjiang Agricultural University

Location: Urumqi, Xinjiang

On October 25, 2020, the School of Science and Technology of Xinjiang Agricultural University was terminatedmerged into the parent university – Xinjiang Agricultural University.

For these schools, candidates and parents should note:

1) Schools that have stopped enrolling students can no longer apply for the exam;

2) Although these independent colleges have to stop running schools, they are also gradually returning to the headquarters (hosting colleges and universities).

2. Why did Bei Shizhu stop running the school?

Beijing Normal University Zhuhai Branch is one of the few independent colleges with a public nature in China. It is managed by the Guangdong Provincial Department of Education, Beijing Normal University and the Zhuhai Municipal Government. Since the establishment of the school in 2001, the school’s strength has been continuously improved, and it has accumulated a certain popularity in the local area and has won many praises from the outside world. Therefore, when the school announced that it would terminate the school, students, parents and teachers did not understand it, and the controversy continued.

However, there are two important reasons why Beijing Normal University Zhuhai Branch has to stop running schools:

1. Land is required for the establishment of the Zhuhai Campus of Beijing Normal University

Beijing Normal University is a well-known 985 university in my country, and it is also the number one normal university in China. Under the current wave of 985 colleges and universities opening campuses in different places (such as the success of Harbin Institute of Technology), Zhuhai City and Guangdong Province hope to welcome another famous school locally to promote the development of local education. Therefore, the establishment of the Zhuhai campus of Beijing Normal University can be described as the general trend. However, the establishment of a school is inseparable from land, and Beijing Normal University Zhuhai Branch has land, school buildings and other resources. At the same time, the construction of the Zhuhai campus of Beijing Normal University will also use the land used for the Beijing Normal University-Hong Kong Baptist University Joint International College which has been reclaimed by agreement.

2. The Ministry of Education continues to promote the process of transferring independent colleges

Since 2020, there has been continuous news of the establishment of independent colleges in my country. In May, the Ministry of Education directly issued the “Implementation Plan on Accelerating the Transfer of Independent Colleges”, which brought a “great acceleration” to the transfer of independent colleges across the country. For a time, independent colleges across the country began to transfer, mainly to private and public colleges, and if the transfer could not be completed, the school could only be terminated.

In a word, even though Beijing Normal University Zhuhai Branch is a good independent college, its fees are always higher, and its educational strength cannot be compared with that of 985 colleges. Therefore, the termination of the school and the integration of Beijing Normal University into Zhuhai Campus of Beijing Normal University is of positive significance for the higher education of Zhuhai City and even the entire Guangdong Province.

Recently, Siemens Digital Industries Group held a media communication meeting in Beijing. Leaders and media teachers reviewed Siemens Digital Industries Group’s “highlight moments” in 2020 and introduced the company’s business plan for 2021.

In 2020, the severe impact of the “black swan” of the new crown epidemic on global economic development is obvious to all, and the industry/manufacturing industry, as an important support for my country’s national economy, has also undergone severe tests. Unexpected problems such as workers being unable to arrive at work, market depression, and changing user needs have become the “last straw” that crushed traditional factories with the outbreak of the epidemic, and made them truly realize the importance of digital transformation. We can see that those companies that have achieved certain results in digital transformation can have sufficient resilience and flexibility in the face of sudden risks and uncertainties, and adjust their business in a timely manner with the help of artificial intelligence, industrial Internet and other technologies.

Recently, the Ministry of Industry and Information Technology issued the “Notice on Printing and Distributing the “Industrial Internet Innovation and Development Action Plan (2021-2023)” to deploy in infrastructure, integrated applications, technological innovation, industrial ecology, security and other aspects. The action plan is under the guidance of the “Guiding Opinions of the State Council on Deepening the “Internet + Advanced Manufacturing Industry” to Develop the Industrial Internet”, and is closely linked with the “Industrial Internet Development Action Plan (2018-2020)” released in 2018. The coordinated promotion of more than 10 ministries and commissions shows the country’s determination to implement the industrial Internet, a major industrial strategy.

Today, my country’s industrial Internet has entered a period of rapid development, and the technology and system systems have become mature, and the industry has successfully landed. Against this background, Siemens Digital Industries Group recently held a media communication meeting in Beijing. Leaders and media teachers reviewed Siemens Digital Industries Group’s “highlight moments” in 2020 and introduced the company’s 2021 business planning.

The Chinese market is booming

Wang Haibin, Executive Vice President of Siemens (China) Co., Ltd. and General Manager of Siemens Greater China Digital Industry Group, said, “In fiscal year 2020, despite the impact of the new crown epidemic, Siemens’ business in the Chinese market still achieved positive growth. At the same time, Siemens China Digital Industries Group achieved double-digit growth in the fourth quarter, which is a strong driver of Siemens’ global business.”

Siemens Digital Industries Group focuses on industrial manufacturing. Its business covers a wide range of product lines in process industry, discrete industry and hybrid industry. It helps customers realize the transformation from automation and standardization to digitalization and intelligence, and uses digital twin technology to build product design and product design. The “digital twin” of the three links of manufacturing and product performance drives production line optimization and product iteration by comparing the data differences between design parameters and actual products.

Based on long-term attention and in-depth research on the Chinese market, Wang Haibin proposed that in the future, Siemens’ digital industrial business will have three major driving forces:

Market-driven: The state has increased investment in the construction of new infrastructure such as 5G, edge computing, cloud computing, and industrial Internet, creating a favorable market environment for the development of the digital industry.

Driven by “internal circulation”: China still has a lot of room for development in inland and western regions. Many customers are migrating from coastal areas to the central and western regions, and the demand for digital transformation is increasing.

Driven by consumer demand: Consumers’ increasing demand for personalized and customized products has stimulated the demand for agile development and flexible production in the industrial manufacturing field, which in turn drives the development of the digital industry.

Over the years, Siemens has actively promoted the application of intelligent manufacturing in the domestic market, provided technical support for the implementation of Industry 4.0, and worked with solution providers and traditional electrical engineering companies to provide users with comprehensive solutions combining OT and IT. In addition, under the guidance of policies, Siemens has gathered scientific research think tanks and manufacturing enterprises to jointly build an ecosystem and jointly promote the digital transformation of China’s industries.

Finally, Wang Haibin shared the new vision of Siemens Digital Industries Group with the media teachers present: “‘We create sustainable industrial innovation for a world we want to live in, today and tomorrow’, we can understand it as everyone wants to live In a better world, this better world needs key innovation support from the industry. Among them, ‘continuous industrial innovation’ is precisely the mission of Siemens Digital Industries Group.”

Build an ecosystem together and create the future of automation

Under the guidance of the Chinese government’s “new infrastructure” policy, the Factory Automation Division has also actively participated in the development of this field. For example, we provide complete solutions for vast data centers, 5G modules, subways and tunnels. In addition, we are also committed to helping Chinese enterprises to carry out digital transformation, especially the construction of digital factories. And it has provided leading end-to-end solutions for the metallurgical industry, the automotive industry, the semiconductor industry, and electric vehicle batteries for a long time, helping all walks of life to build digital factories.

Joerg Westerholt, Vice President of Siemens (China) Co., Ltd. Digital Industry Group and General Manager of Factory Automation Division, proposed that looking forward to the future, the automation market is divided into three categories: automation solutions for simple applications, suitable for all applications and Totally integrated automation and digital solutions for the industry, as well as the automation of the future.

in:

For the automation market of simple applications, the Factory Automation Division can meet the needs of customers in the broad market and provide a complete set of cost-effective solutions, such as SMART PLC, SMART IPC, SMART HMI (economical PLC, economical industrial computer, economical human-machine interface) ). In this area, customers are very price-sensitive and Siemens is very competitive.

In the standard automation or high-end automation market, function and efficiency are the core content. Siemens has a comprehensive SIMATIC product portfolio and ensures efficient performance, providing different products and solutions for the entire industry. The safety PLC of Siemens can guarantee the daily safe production of workers, and the redundant PLC can ensure the machine runs with high reliability 24 hours a day.

Siemens continues to explore the “automation of the future” and is committed to being “a major contributor to this trend”. In the future, the Factory Automation Division of Siemens Digital Industries Group will build an ecosystem based on edge computing, organically combine OT and IT, and leverage its AI capabilities to assist customers in developing AI applications suitable for enterprise business, helping customers improve productivity and product quality , to achieve more flexible and safe efficient production.

Wei Yuege introduced in a subsequent interview that Siemens can develop highly customized, business-oriented APPs together with customers, customers provide processes, and Siemens provides automation knowledge. Siemens has established a related team for this purpose. The main business is to assist customers to jointly develop industrial edge APPs. On the basis of APPs, richer business models can be expanded to build a long-term ecosystem.

More blossoms to fully assist the digital transformation of enterprises

Yao Jun, Vice President of Siemens (China) Co., Ltd. Digital Industry Group and General Manager of Process Automation Division, introduced to the participating media how Siemens has helped factories in chemical, sewage treatment, pharmaceutical and other fields increase efficiency and quality during the epidemic:

Water industry: The Web-based control system SIMATIC PCS neo can realize remote debugging and deployment, which solves the problem that technicians cannot be present during the epidemic. In addition, Siemens also launched the DPS digital pumping station, adding functions such as diagnostic prediction and maintenance.

Sewage treatment: Toxic gases released from underground sewage can easily cause harm to inspectors. Siemens uses RTLS technology to monitor the positioning of inspectors in real time. If they stay for a long time, there is a danger of early warning, and the accuracy can reach 10cm.

Pharmaceutical field: Siemens helps companies such as Sinopharm Rongsheng, Shandong Ruiying, and Beishengyan to establish digital production lines.

Petrochemical industry: Siemens helped Sinopec Qingdao Refinery & Chemical Co., Ltd. successfully deploy the SiePA predictive maintenance system to help customers improve operation and maintenance efficiency; realize real-time optimization of process models through digital twins.

Industrial communication and identification solutions: As an indispensable and important part of digitalization, it is not only used in the process industry, but also in discrete industries such as logistics to provide customers with complete communication solutions from OT to IT, including wired, wireless, AGV and other technologies .

In the future, Siemens will increase investment in the chemical industry, and use digital means to help fine chemical, biochemical and other sub-sectors achieve cost reduction and efficiency improvement.

Native digitization helps factories rapidly increase production capacity

Li Lei, general manager of Siemens CNC (Nanjing) Co., Ltd., said: In fiscal year 2020, in the face of the improvement of national living standards and changes in product demand, the Siemens Motion Control Division adjusted its strategy in a timely manner. Through intensive cultivation in the material manufacturing, textile and other industries, it has achieved strong positive sales growth. In the future, Siemens will cooperate with partners and experts in various industries to promote combined products in aerospace, automobile manufacturing and other fields.

Li Lei also introduced the new Siemens Nanjing factory, which is about to be completed and put into production, to the participating media, which is the first native digital factory of Siemens. The so-called “native digitization” refers to the establishment of a simulation model from the first day of the project. The entire process from demand analysis to conceptual design, Module design, detailed design, construction, and operation management of the plant is entirely based on digital twin technology. In this process, the general data platform can call all data for simulation, simulation, practice and adjustment, so as to realize real-time monitoring and agile feedback in the operation process.

For example, in the factory planning and design stage, based on the modeling and simulation functions of Siemens digital industrial software, the simulation model of each design stage is established, and then based on the output rate, equipment utilization rate, personnel work efficiency, yield rate, energy utilization rate, Indexes such as material flow efficiency, personnel walking distance, and in-process inventory are used to find the optimal solution in the model verification.

According to Li Lei, Siemens’ native digital factory will increase production capacity by nearly 2 times, shorten the time to market by 20%, increase the efficiency of personnel utilization by 20%, and increase the utilization rate of factory space by 40%.

Keep up with the demand and work with customers to innovate together

Wang Biao, Vice President of Siemens (China) Co., Ltd. Digital Industry Group and General Manager of Customer Service Division, said, “Whether it is before or after the epidemic, the mission of Siemens Industrial Services has not changed, that is, to closely focus on customer needs and work with customers. Innovate and provide customers with digital services in four aspects: equipment, assets, people, and processes.”

During the epidemic, engineers were unable to arrive at the site in time, so Siemens developed a remote service “Smart Card”, which allows engineers to solve on-site problems remotely in the background, and provides customers with many virtual products including training through the e-commerce platform.

After the resumption of work, Siemens helped customers in the catering industry deploy an intelligent food delivery system to reduce labor and ensure safety after resumption of production; help customers in the automotive, steel and other industries to complete predictive analysis, manage factory production information, and achieve “more, faster, better savings”. “The goal.

In the future, Siemens will replicate and promote the experience accumulated in the process of digital transformation of global factories through the “CIO” model (ie C-consultation, I-implementation, O-operation optimization), and continue to work with partners to develop the industry Digital service, embrace the digital future!

Create a closed loop to enhance the core competitiveness of software

Liang Naiming, global senior vice president of Siemens Digital Industry Software and managing director of Greater China, shared the achievements of Siemens’ industrial digital software business in 2020 and the outlook for 2021 with the participating media online. He introduced, “Software is something that cannot be seen or touched. It is not the same as hardware, but in fact, the software strength of many enterprises is the core competitiveness.”

The latest Xcelerator launched by Siemens includes the entire process from product design, production planning to product manufacturing, production execution, and optimization iterations, creating a closed loop of product application, factory ergonomics and production safety, and integrating all data with multidisciplinary physical operations.” Tie” in the whole life cycle of the product, and iterate and innovate the product continuously within this closed loop.

Liang Naiming said: “Siemens is an industrial software company that can provide end-to-end products and solutions. Through software, the complete manufacturing cycle of product manufacturing, production planning, production execution, and safety production is covered by Xcelerator. At present, Siemens is a leading As an industrial software provider, we can assist in integrating different products of different manufacturers to achieve coordinated operation, so that customers can focus on their own industrial research and development and product manufacturing, and provide customers with the greatest value.”

At the end of the exchange meeting, Wang Haibin, Executive Vice President of Siemens (China) Co., Ltd. and General Manager of Siemens Digital Industries Group in Greater China, when answering questions from reporters, took the upgrade of an elephant into a “perfect elephant” as an example, explaining the era of Industry 4.0. Every link of production and manufacturing should be upgraded to future technologies under the blessing of digitalization, so as to realize the interconnection of data, create a better computer-aided intelligent manufacturing model, and then form a higher level of intelligence, and upgrade the factory to ” The perfect factory”. In the future, Siemens Digital Industries Group will continue to focus on factory automation, digitalization and intelligent industries, and help China’s manufacturing industry complete the upgrade of the “perfect elephant”!