“JESD204B is a recently ratified JEDEC standard for the serial data interface between converters and digital processing devices. It is a third-generation standard that addresses some of the flaws of the previous version. The benefits of this interface include less board space for data interface routing, lower setup and hold timing requirements, and smaller converter and logic packages. New analog/digital converters from several suppliers use this interface, such as ADI’s AD9250.

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JESD204B is a recently ratified JEDEC standard for the serial data interface between converters and digital processing devices. It is a third-generation standard that addresses some of the flaws of the previous version. The benefits of this interface include less board space for data interface routing, lower setup and hold timing requirements, and smaller converter and logic packages. New analog/digital converters from several suppliers use this interface, such as ADI’s AD9250.

Compared to existing interface formats and protocols, the JESD204B interface is more complex and subtle, and some difficulties must be overcome to realize its benefits. Like other standards, for this interface to be more popular than commonly used interfaces such as single data rate or double data rate CMOS/LVDS, it must work seamlessly. Although the JESD204B standard was developed by JEDEC, some specific information still needs to be clarified or may be scattered across multiple references. Also, it would be extremely helpful for users to have a concise guide that outlines the standard, how it works, and how to troubleshoot it.

This article explains how a JESD204B-compliant ADC interfaces with an FPGA, how to tell if it’s working properly, and, perhaps more importantly, how to troubleshoot when there’s a problem. The troubleshooting techniques discussed in this article can use common test and measurement equipment, including oscilloscopes and logic analyzers, as well as Xilinx^®ChipScope or Altera^®Software tools such as SignalTap. Interface signaling is also clarified to enable visualization of signaling using one or more methods.

Overview of JESD204B

The JESD204B standard provides a method of interfacing one or more data converters with a digital signal processing device (usually an ADC or DAC to an FPGA), which is a higher speed serial line interface. The interface operates at speeds up to 12.5 Gbps/lane and uses a framed serial data link with embedded clock and alignment characters. It simplifies the implementation of high-speed converter data interfaces by reducing the number of traces between devices, reducing trace matching requirements, and eliminating setup and hold timing constraints. Since the link needs to be established before data can be transmitted, new challenges exist and new techniques must be employed to determine if an interface is working properly and what to do if it fails.

The JESD204B interface establishes a synchronization link through three phases: Code Group Synchronization (CGS), Initial Lane Synchronization (ILAS), and the data transfer phase. The link requires the following signals: a shared reference clock (device clock), at least one differential CML physical data electrical connection (called a “lane”), and at least one other synchronization signal (SYNC~ and possibly SYSREF). Which signals are used depends on the subclass:

• Subclass 0 uses device clocks, channels, and SYNC~.
• Subclass 1 uses device clocks, channels, SYNC~, and SYSREF.
• Subclass 2 uses device clocks, channels, and SYNC~.

Subclass 0 is sufficient in many cases and is therefore the focus of this article. Subclasses 1 and 2 provide methods to establish deterministic latency, which is important in applications that require synchronization of multiple devices or where system synchronization or fixed delays are required, such as an event in a system that requires a known sampling edge, Or an event must respond to an input signal within a specified time.

Figure 1 shows a simplified JESD204B link from a transmitter device (ADC) to a receiver device (FPGA), with data traveling from one ADC over one channel.

Figure 1. JESD204B link diagram: An ADC interfaces with an FPGA through one channel.

While the JESD204B specification has many variables, some variables are particularly important for link establishment. These key variables are as follows (note: these values ​​are usually denoted as “X − 1”):

• M: Number of converters.
• L: Number of physical channels.
• F: Number of 8-bit bytes per frame.
• K: The number of frames per multiframe.
• N and N’: respectively the converter resolution and the number of bits (multiples of 4) used per sample. The value of N’ is equal to the N value plus the number of control and padding data bits.

Subclass 0: Synchronization step

As mentioned above, many applications can use the relatively simple subclass 0 mode of operation, which is also the simplest mode for establishing and verifying a link. Subclass 0 establishes and monitors synchronization through three phases: the CGS phase, the ILAS phase, and the data phase. Graphs associated with each stage Display data in different formats, which can be viewed on an oscilloscope, logic analyzer, or FPGA virtual I/O analyzer such as Xilinx ChipScope or Altera SignalTap.

Code Group Synchronization (CGS) Phase

The most important parts of the CGS phase that can be observed on the link are shown in Figure 2, and the 5 highlighted points in the figure are illustrated below.

• The receiver issues a synchronization request by pulling the SYNC~ pin low.
• The transceiver transmits unscrambled /K28.5/ symbols (10 bits per symbol) starting with the next symbol.
• Synchronize when the receiver receives at least 4 consecutive /K28.5/ symbols without errors, then pull the SYNC~ pin high.
• The receiver must receive at least 4 error-free 8B/10B characters, otherwise the synchronization will fail and the link will remain in the CGS phase.
• The CGS phase ends and the ILAS phase begins.

Figure 2. Logic output of a JESD204B subclass 0 link signal at the CGS stage (assuming two channels, two ADCs in one device).

The /K28.5/ character is also known as /K/ in the JESD204B standard, as shown in Figure 3. The standard requires DC balancing. With 8B/10B encoding, a balanced sequence containing equal numbers of ones and zeros on average can be achieved. Each 8B10B character may have a positive (more 1’s) or negative (more 0’s) bias, the parity of the current character is determined by the polarity bias of the previously sent character, this is usually done by alternately sending words of positive parity with negative parity Sex words to achieve. The figure shows both polarities of the /K28.5/ symbol.

Figure 3. The logical output of the K28.5 character and how it propagates through the JESD204B Tx signal path.

Focus on the following points:

• The serial value represents the 10-bit logic level transmitted through the channel and can be seen by an oscilloscope measuring the physical interface.
• The 8B/10B value represents the logical value (10 bits) transmitted over the channel and can be seen by a logic analyzer measuring the physical interface.
• Data values ​​and data logic represent the logic levels of symbols within the JESD204B transceiver block prior to 8B/10B encoding, which can be seen with FPGA logic analysis tools such as Xilinx ChipScope or Altera SignalTap.
• Symbol Indicates the hexadecimal value of the character to be sent, paying attention to the parity of the PHY layer.
• Character Indicates a JESD204B character as referred to in the JEDEC specification.

ILAS stage

The ILAS stage has 4 multiframes, allowing the receiver to align the lanes from all links, as well as verify link parameters. To reconcile traces of different lengths and character skew caused by the receiver, the channels must be aligned. The 4 multiframes are closely connected (Figure 4). ILAS always transmits without scramble, regardless of whether the scrambled link parameter is enabled or not.

Figure 4. Logic output of JESD204B subclass 0 link signals during the ILAS phase.

After the SYNC signal changes from low to high, it enters the ILAS stage. After the sending Module has tracked (inside the ADC) a complete multi-frame, it starts to send 4 multi-frames. Insert padding data in the required characters to transmit a complete multiframe (Figure 4). 4 multiframes include:

• Multiframe 1: with /R/ character[K28.0]Start with the /A/ character[K28.3]Finish.
• Multiframe 2: Begins with /R/ character followed by /Q/ [K28.4]character, followed by 14 configuration octets of link configuration parameters (Table 1), ending with the /A/ character.
• Multiframe 3: Same as Multiframe 1.
• Multiframe 4: Same as Multiframe 1.

Figure 5. /K/ character[K28.5]/R/ character[K28.0]/A/ character[K28.3]and /Q/ characters[K28.4]picture.

Table 1. CONFIG table for ILAS multiframe 2 (14 JESD204B configuration parameter 8-bit words)

The frame length can be calculated using the JESD204B parameters:

(S) × (1/sample rate).

meaning:

(samples/converter/frame) x (1/sample rate)

Example:

A converter with a sampling rate of 250 MSPS and one sample per converter per frame (note: “S” is 0 in this example because it is encoded as a binary value -1) has a frame length of 4 ns.

The multiframe length can be calculated using the JESD204B parameters:

meaning:

(number of samples/converter/frame) × (number of frames/multi-frame) × (1/sample rate)

Example:

A converter with a sampling rate of 250 MSPS, one sample per converter per frame, and 32 frames per multiframe has a multiframe length of 128 ns.

Data stage (enable character replacement)

During the data transfer phase, frame alignment is monitored by control characters. Perform character replacement at the end of the frame. During the data phase, there is no additional overhead for data or frame alignment. Character replacement allows alignment characters to be sent at frame boundaries, only if the last character of the current frame can be replaced with the last character of the previous frame. This facilitates (occasionally) confirmation that the alignment has not changed since the ILAS sequence.

Character substitution is performed on the sender when:

• If scrambling is disabled, the last octet of the frame or multiframe is equal to the octet of the previous frame.
• If scrambling is enabled, the last octet of a multiframe is equal to 0x7C, or the last octet of a frame is equal to 0xFC.

The transmitter and receiver each maintain a local multiframe counter (LMFC), which continues to count up to (F × K) − 1, then wraps around to “0” and restarts counting (ignoring the internal word width). Sending a common (source) SYSREF to all transmitters and receivers, these devices use SYSREF to reset their LMFCs so that all LMFCs should be synchronized (within one clock cycle) to each other.

After releasing SYNC (seen by all devices), the transmitter starts ILAS the next time (Tx) the LMFC wraps around to 0. If F × K is set appropriately, greater than (transmitter encoding time) + (line propagation time) + (receiver decoding time), the received data will be propagated out of the receiver’s SERDES before the next LMFC. The receiver will put data into the FIFO and then start outputting data at the next (Rx) LMFC boundary. This known relationship between the transmitter’s SERDES input and the receiver’s FIFO output is called deterministic latency.

What can go wrong?

JESD204B can be said to be a complex interface standard with many subtleties in operation. Finding out why it’s not working requires a good understanding of the possible scenarios:

Stuck in CGS mode: if SYNC remains logic low; or if the pulse high duration is less than 4 multiframes:

Check the board, no power up:

• The SYSREF and SYNC~ signals should be DC coupled.
• With the board unpowered, check that the board SYNC~ connection from the SYNC~ source (usually from an FPGA or DAC) to the SYNC~ input (usually an ADC or FPGA) is good and low impedance.
• Make sure that the pull-down or pull-up resistor is not the dominant factor in the signal transmission, eg too small or shorted to drive properly.
• Verify that the differential pair traces (and cables, if used) of the JESD204B link are matched.
• Verify that the differential impedance of the traces is 100 Ω.

Check the board, power up:

• If there is a buffer/translator in the SYNC path, make sure it is working properly.
• Verify that the SYNC~ source and on-board circuitry (SYNC+ and SYNC-, if differential) are configured correctly to produce logic levels that meet the requirements of the SYNC~ sink device. If the logic levels are not compatible, the source and sink configuration should be checked to identify the problem, otherwise, consult the device manufacturer.
• Verify that the JESD204B serial transmitter and board circuitry are configured correctly to produce the correct logic levels required by the JESD204B serial data receiver. If the logic levels are not compatible, the source and sink configuration of the circuit should be checked to identify the problem. Otherwise, consult the device manufacturer.

Check the SYNC~ signal:

• If SYNC~ is a static logic level, the link will stay in the CGS phase. There may be a problem with the data being sent, or the JESD204B receiver is not decoding the samples properly. Confirm that the /K/ character was sent, confirm the receive configuration settings, confirm the SYNC~ source, check the board circuitry, consider overdriving the SYNC~ signal and force the link into ILAS mode to identify link receiver and transceiver problems. Otherwise, consult the device manufacturer.
• If SYNC~ is a static logic high, verify that the source device is properly configured with the SYNC~ logic level. Check pull-up and pull-down resistors.
• If the SYNC~ pulse goes high and then returns to a logic low state for less than 6 multiframe periods, the JESD204B link advances from the CGS phase to the ILAS phase, but stays in the latter phase. This probably means that the /K/ character is correct and the basic functionality of the CDR is normal. See the “ILAS Troubleshooting” section.
• If SYNC~ goes high for more than 6 multiframe periods, the link advances from the ILAS phase to the data phase, but fails in the latter phase; see “Data Phase” for troubleshooting tips part.

Check serial data

• Verify that the transceiver’s data rate is the same as the receiver’s expected rate.
• Measure the channel with a high impedance probe (differential probe if possible); if the characters look wrong, make sure the channel differential traces are matched, the return path on the PCB is not interrupted, and the device is properly soldered to the PCA. Unlike the (seemingly) random characters of the ILAS and data stages, the CGS characters are easy to identify on an oscilloscope (if using a sufficiently fast oscilloscope).
• Verify the /K/ character with a high impedance probe.

• If the /K/ character is correct, the transceiver side of the link is functioning properly.
• If the /K/ character is incorrect, there is a problem with the transceiver device or the board channel signal.
• If DC coupled, verify that the transmitter and receiver common mode voltages are within the required range of the device.

• Depending on the implementation, the transmitter common mode voltage may range from 490 mV to 1135 mV.
• Depending on the implementation, the receiver common-mode voltage may range from 490 mV to 1300 mV.
• Verify the transmitter CML differential voltage on the data channel (note that the CML differential voltage is equal to twice the voltage swing on each side of the signal).

• For speeds of 3.125 Gbps and below, the transmitter CML differential voltage range is 0.5 V pp to 1.0 V pp.
• For speeds of 6.374 Gbps and below, the transmitter CML differential voltage range is 0.4 V pp to 0.75 V pp.
• For speeds of 12.5 Gbps and below, the transmitter CML differential voltage range is 0.360 V pp to 0.770 V pp.
• Verify the receiver CML differential voltage on the data lane (note that the CML differential voltage is equal to twice the voltage swing on each side of the signal).

• For speeds of 3.125 Gbps and below, the receiver CML differential voltage range is 0.175 V pp to 1.0 V pp.
• For speeds of 6.374 Gbps and below, the receiver CML differential voltage range is 0.125 V pp to 0.75 V pp.
• For speeds of 12.5 Gbps and below, the receiver CML differential voltage range is 0.110 V pp to 1.05 V pp.
• If the pre-emphasis option is present, enable it and observe the data signal on the data path.
• Make sure the transmitter and receiver have the same M and L values, otherwise the data rates may not match. For example, the expected serial interface data rate for M = 2 and L = 2 is half that of M = 2 and L = 1.
• Make sure that the device clocks entering the transmitter and receiver are phase locked and at the correct frequency.

If SYNC goes high for about 4 multiframes, stay in ILAS mode:

• Link parameter conflict
• Verify that the link parameters are not offset by 1 (many parameters are specified as values ​​minus 1).
• Confirm that the ILAS multi-frame transmission is correct, and confirm that the link parameters of the transceiver device, the receiving device, and the ILAS second multi-frame transmission are correct.
• Calculate the expected ILAS length (tframe, tmultiframe, 4 × tmultiframe), confirming that the ILAS has attempted approximately 4 multiframes.
• Verify that all channels are functioning properly. Make sure there are no multi-channel/multi-link conflicts.

Entering the data phase but occasionally the link resets (returning to the CGS and ILAS phases first, then to the data phase):

• Invalid setup and hold times for periodic or bandgap periodic SYSREF or SYNC~ signals.
• Link parameter conflict.
• Character substitution conflicts.
• Scrambling issues (if enabled).
• Channel data corruption, noise, or jitter may force the eye to close.
• Excessive jitter in a spurious clock or device clock.

Other general tips for troubleshooting links:

• Run converters and links at the lowest speed allowed so that more readily available low-bandwidth measurement instruments can be used.
• Set the minimum allowed M, L, K, S combinations.
• Use test mode when possible.
• Use subclass 0 for troubleshooting.
• Disable scrambling when troubleshooting.

This troubleshooting guide is not exhaustive, but provides a good basic framework for engineers working with JESD204B links and wishing to learn more.

The above is an overview of the JESD204B specification and provides useful information about the link. Hopefully, engineers working on this latest high-performance interface standard will benefit from this and help with troubleshooting.