When I first graduated, I was young and frivolous, thinking that I could be on my own and that what I had learned in the temple was enough to meet the needs of the industry. However, in the later work process, I met a lot of great people and learned a lot from them. I summarized the knowledge structure that an IC design engineer needs to have, and I want to share it with you.

　　Skill list

As a truly qualified digital IC design engineer, you always need to keep learning more advanced knowledge and technology. Therefore, the skills listed here will never be complete. I try to update this list once a year. If you think this list is not comprehensive, you can leave a message under this article, and I will try to complete it as much as possible.

Language class: Verilog-2001/ VHDL, SystemVerilog/ SystemC, Makefile/ Perl/ Python/ Shell, Tcl

Tools: NCVerilog/VCS/ModelSim, SimVision/DVE/Verdi, Vim/Emacs, SVN/CVS/Git, Microsoft Office

Platform class: Windows, Linux, OS X

Other bonus projects: MATLAB, ISE/ Synplify/ Vivado/ Quartus, LEC/Formality, VMM/ UVM, ESL, ZeBu Server, JIRA/ Confluence, C/ Assembly Language, Computer Architecture/ ARM Architecture/ MIPS Architecture

　　why & how

A) Verilog-2001/VHDL

The emphasis here is on Verilog-2001 rather than Verilog-1995, because many new features are specified in Verilog-2001, thus resulting in better code style.

I gave a detailed example of the new interface syntax in the article What is good Verilog code style. This new interface method is simpler to modify, and it is more convenient to use when instantiating modules. Unlike the old version of the interface syntax, an interface needs to be described in three times, which increases the number of lines of code for no reason and is difficult to read and modify. , especially when the number of interfaces of a Module exceeds the Display range of a screen, this advantage of Verilog-2001 is more prominent.

The biggest problem with learning Verilog is that many domestic ones are not well written. Many examples in the book exist to illustrate grammatical features, without any practical value, and even many codes are wrong (the meaning of error here is not Not that he is grammatically wrong, but that he is not synthesizable and cannot be implemented equivalently with digital circuits).

Therefore, for learning Verilog, my suggestion is to find a book similar to the grammar manual, read the basic grammar in a hurry, and figure out the module definition, interface definition, module instantiation, register definition, line definition, how to always block After writing these basic contents, go to the OpenCores website to download the complete open source project code that has been verified by FPGA for learning. First try to understand the code written by others, and then try to imitate it yourself. If there is a problem that you don’t understand, then go to the Internet to search for the answer in a targeted manner.

The biggest difference between Verilog language and software language is that because it is used to describe circuits, its writing method is very fixed, because circuit changes are very limited. When learning Verilog, many times we are not learning the language itself, but learning its corresponding circuit features and how to describe the circuit.

You can’t write Verilog well if you don’t have circuits in mind. Starting from the basics, it is very important to accumulate small circuit description methods such as timers and decoders. Verilog encourages innovation in circuits, not in description methods. Therefore, even the most powerful Verilog master in the world, the Verilog code syntax he wrote is very common, and his creativity lies in how to combine these basic small circuits.

Although I don’t know much about VHDL, VHDL is still the mainstream RTL design language in many European countries. The rigor of the VHDL language is better than that of Verilog. Unlike Verilog, there are a large number of grammatical statements that can never be synthesized, which is easy to mislead newcomers (the code that passes the simulation is reported in the FPGA synthesis error, or the FPGA implementation results are inconsistent with the simulation) . Although VHDL and Verilog can be converted into each other, there are still many problems in the conversion process, which cannot be fully automated. I wrote a topic about this before: How to convert VHDL to Verilog. Interested students can go and see.

B) SystemVerilog/ SystemC

Both languages ​​exist for verification. As an IC design engineer, verification knowledge is not necessary, but mastering the basic verification methodology can help improve your debug efficiency and results. I once introduced a verification method I summarized in detail in the article on how to quickly build a module verification platform. This method is implemented based on SystemVerilog syntax. Since SystemVerilog is fully compatible with Verilog, just like C++ is compatible with C language, it is not difficult to learn SystemVerilog (or SV).

SystemVerilog is an object-oriented language. Its original intention is to build a verification platform. The mainstream VMM/UVM methods are also implemented based on SystemVerilog, so students who are determined to become IC verification engineers, in-depth study of SystemVerilog and popular methodology learning is essential.

For those who only want to do IC design, SystemVerilog is also worth learning. Not to mention the debug methods mentioned earlier in this article for improving verification efficiency, even if it is just for good design, SystemVerilog is very useful. In many developed countries in Europe and America, many of the world’s top IC design companies have already begun to use SystemVerilog for RTL design. Since many new syntaxes such as always_ff and always_comb are added to SystemVerilog to explicitly indicate the intention of the synthesis circuit, the code is more readable, the ambiguity is reduced during the synthesis process, and the synthesis results and design intentions are guaranteed as much as possible. consistency. From another point of view, the addition of assertTion also greatly improves the debug efficiency of the code, which is very helpful to locate the initial point of error in the large-scale data interaction process. Students who do not know it can spend more time to study it. .

C) Makefile/ Perl/ Python/ Shell

The above four are scripting languages ​​commonly used by IC design engineers. It seems that they have nothing to do with the professional ability of IC design. However, because the professional tools in this industry are very expensive and the project requirements vary greatly, mastering one A handy scripting language will greatly help you improve your work efficiency. If you haven’t tried writing your own scripting language, ask yourself, have you ever stayed up late at night trying to complete a batch of simulation use cases? Have you ever been blinded by comparing tens of thousands of data? Crazy because of changing the bit width of a global signal? What if you want to convert a hex type data file to the special format required by the memory model? Yes, if you have mastered the scripting language, these strange requirements above It’s not a problem, just leave the repetitive and meticulous manual work to the computer. The slogan I have always believed in is: as long as you have done something once, there is no need to repeat it a second time.

If you’ve used a platform or script developed by other engineers at work, it’s likely written in these 4 languages. If the method of executing the script is make run, then it is very likely that you are using a Makefile script; if the method of executing the script is source run, then this should be a script written in the Shell language; if it is other cases, then it depends on the specific How is the first line of the script written? Makefile and Shell languages ​​are easier to use than Perl/Python, and they are simpler to write, which are more suitable for some very simple batch tasks. Perl’s strength lies in its powerful text processing capabilities and omnipotent CPAN library, which can meet your various willful needs at any time. The advantage of Python is better maintainability.

Regarding the importance of scripting languages, you can go here to see related discussions: What are the uses of scripting languages ​​such as Perl in IC design?

D) Tcl

Strictly speaking, Tcl is a very simple and simple language, and the difficulty in learning it is that just mastering its syntax is far from enough. This situation is a bit similar to javascript. If you use js to develop web pages, then you must have a deep understanding of DOM and HTML; if you use js to develop games, then you must have a deep understanding of various knowledge of the Unity3D engine; if you use js to develop Web App, then you must be able to use various libraries of node.js and common server-side frameworks.

Languages ​​are always just tools, and this phrase is more than appropriate in Tcl. In the field of IC design, Tcl is a very common language. It can be used to describe timing and pin constraint files, UPF information, and can also be used to build a simple working platform. It is not only the default scripting language supported by many EDA tools in the IC field, but also the file format for configuration and output of these tools. Therefore, being able to read Tcl and master the basic syntax of Tcl language can help you use EDA tools better.

However, success is also Xiao He defeated Xiao He, as mentioned at the beginning of the previous article, just mastering the syntax of Tcl is far from all. Different EDA tools provide different command and parameter support for Tcl scripts. Whenever you need to write Tcl scripts for a new tool, you must read the official user manual to understand the tool support The Tcl command structure can ensure that the script written can be executed correctly.

E) NCVerilog/ VCS/ ModelSim/ iVerilog

The above three are relatively mainstream simulation tools in the industry. Both NCVerilog and VCS only support the Linux platform, while ModelSim seems to support both the Linux platform and the Windows platform. But either way, I want you to realize two things:

First, the emulator and the waveform viewer are two different things. This entry only introduces the emulator. The working principle of the emulator is very different from that of the waveform viewer. At the same time, due to the IEEE specification of the standard waveform file *.vcd format , any simulator can be used in combination with the arbitrary waveform viewer.

Second, the emulator usually does not have a graphical interface. In order to use the emulator better, you should familiarize yourself with the user manuals of your commonly used emulators, understand some command-line parameters for common requirements, and at least understand the following: how to Specify the type of files to be compiled, how to specify the list of compiled files, how to specify the index directory, how to specify the simulation precision, how to specify temporary macro variables, how to specify the severity level of syntax checking, how to mix and compile projects written in multiple languages, how to Call the pli interface of different waveform generation tools, how to perform post-simulation with SDF back-labeling, etc.

The functions of different emulators are actually similar, but can you be invincible by mastering only one emulator? Of course not. In actual projects, we often use third-party IP cores. Sometimes, for confidentiality reasons, third-party IP cores are provided in the form of encrypted binary files. What does the encrypted binary file look like?

They are generally named in “*.vp” format. The beginning of the file is standard Verilog syntax, but after a line of comment, it all becomes garbled. Usually the comment line before the garbled character specifies the emulator type supported by the encrypted binary. So you see, if you are a heavy VCS user, and one day the project manager suddenly shoves you an encrypted file that only supports NCVerilog, there will be thousands of grass and mud horses whizzing through your heart.

F) SimVision/ DVE/ Verdi/ ModelSim/ gtkWave

Corresponding to the above simulators, the above three are also mainstream waveform viewing tools in the industry. All waveform viewers must support the standard waveform file *.vcd format, but due to the poor storage performance of *.vcd format and too much redundant information, various waveform viewing tools have launched their own exclusive supported waveforms File formats, such as DVE’s *.vpd, Verdi’s *.fsdb, ModelSim’s *.wlf, SimVision’s *.shm, etc. Usually the file formats exclusively supported by the waveform viewing tool have higher compression ratios.

For example, a waveform in *.vcd format of about 1G is usually only about 40MB after converting to *.vpd format, and it is usually smaller after converting to *.fsdb. Therefore, convert the standard waveform file *.vcd to other compressed formats More conducive to data backup.

If you want to not produce *.vcd during the simulation process, but directly generate other waveform viewer-specific formats with higher compression rates, you need to call the pli interface provided by the corresponding tool, and at the same time cooperate with the system function calls in the test platform code (such as $fsdbDumpOn, etc.) to complete.

G) Vim/Emacs

I often see some Verilog newcomers asking such a ridiculous question: “What kind of software do you use for general Verilog programming?

First of all, Verilog is a circuit description language, which may be closer to the circuit diagram in nature. At least this description process should not be said to be “programming”.

Secondly, there is no special software for writing Verilog. Most engineers in the industry use primitive and rough text editors such as Vim or Emacs to write Verilog code. If you want, you can use Notepad or Texteditor to write it. Just if you have a deep understanding of Vim or Emacs, you will naturally understand why so many people choose them – to improve efficiency.

1. Have you ever been scolded by the boss after writing the code because you did not put all the reg and wire definitions in the same location of the file (such as line 38)? If you use the Vim editor, just use : g%^s*regs*%m 38 plus: g%^s*wires*%m 38 is fine.

2. Have you ever been asked to delete all comments in a file? Just: %s%//.*$%%g.

3. Have you ever needed to instantiate a module 256 times, and then you can’t use the for loop directly because of a little difference in each instantiation? It doesn’t matter, with the qq recording function, you only need to operate it once, and then use 256@q You can automatically repeat your actions 256 times.

4. Have you ever encountered a broken keyboard, the “a” key often fails or even does not respond? It doesn’t matter, use: inoremap ‘a’ to remap the ‘ key to the a key.

There are almost too many examples of this, see Vim Practical Tips for Verilog for more.

So, the biggest advantage of using Vim or Emacs is that you will feel that your brain is busier than your hands, because it only takes a very short time from you to think clearly to write the code. You can devote all your energy to the content of the code, rather than the mechanical process of entering the code, which is like using a typewriter instead of a brush. As long as you can describe things clearly with programming, Vim can quickly complete them for you, and the premise is that you must first learn a lot of Vim commands and regular expressions to ensure that your expressions can be correctly understood by the editor.

G) SVN/CVS/Git

The above three are currently relatively mainstream “version management” tools. What is version management?

In short, it is a tool for recording and querying file version changes, usually deployed on public servers to ensure data security and recovery. At the beginning of the project, the root directory of version management needs to be created first, and then different engineers add their own design files one by one to the subdirectories of version management for the first time.

In the process of project execution, whenever someone modifies a file, they need to upload the code and annotate the changes through the version management tool. The version management tool will automatically check whether the changes conflict with the latest version on the server (conflict means that , in the process of the engineer changing this file, someone else also made changes to the same line of code in the file and uploaded a new version), if there is no conflict, the newly uploaded changes will be automatically merged into the current latest version, On the contrary, the conflicting parts are compared and displayed, so that the engineer can manually judge how to merge the content of the conflicting line, and re-upload it after resolving the conflict.

H) ISE/ Synplify/ Vivado/ Quartus

Both ISE and Vivado are FPGA tools under Xilinx. Among them, ISE is relatively old, and the official update has been stopped. The latest version is 14.7, and Vivado, as a new generation of FPGA tools, has been continuously updated. Quartus is an FPGA tool under Altera, and its functions are similar to ISE/Vivado. The author does not have much contact with FPGA tools on weekdays, but from the limited contact experience, Quartus is more suitable for learning than ISE/Vivado, the entry threshold is lower, and the operation interface is easier to learn (but do not Use the waveform simulation tool that comes with Quartus below version 6.2, that’s garbage).

I) Windows/ Linux/ OS X

It is believed that most people’s personal computers use the above system or other systems similar to the above system. For the above three systems, for professional digital IC front-end designers, the convenience of work (note that it is the convenience of professionals, not the steepness of the learning curve. Work efficiency help) from convenient to difficult are: Linux > Windows > OS X.

Under Windows, the tools you may need are Cygwin (simulated Linux shell, with most GNU tools), Modelsim, Debussy (the version renamed Verdi has no corresponding Windows version), Quartus, ISE, etc. Under Linux, tools you may need include Bash/Csh/Tcsh, Modelsim, Quartus, ISE, VCS, Simvision, DVE, NCVerilog, Formality, LEC, Synplify, etc. Under OS X (where I am unfortunately located), the only tools you can use are Bash/Csh/Zsh, iVerilog, gtkWave.

From the above content, it is not difficult to see that in terms of the diversity of tools, Linux is one of the main reasons why most IC development companies choose to deploy their servers under Linux. For personal computers, most students will choose to use virtual machines to take into account the choice of tools for different platforms. Personally, it is recommended that you better understand the solutions of other platforms on the premise of being proficient in the Linux platform and its tools.