Lessons learned from real-world applications: How to drive the gates of wide-bandgap semiconductor devices

When designing gate drive circuits for silicon MOSFETs or IGBTs, engineers always have to make precise judgments about the long-term cost/performance trade-off. The designer’s understanding of the specific characteristics of the selected switch helps in making decisions, such as whether to use an isolated or non-isolated driver, and the maximum propagation delay acceptable in the application. Decades of experience developing these circuits provide a wealth of expertise, literature, and best practices to draw upon.

By Riccardo Collura, EMEA Vertical Manager (Power), Future Electronics

When designing gate drive circuits for silicon MOSFETs or IGBTs, engineers always have to make precise judgments about the long-term cost/performance trade-off. The designer’s understanding of the specific characteristics of the selected switch helps in making decisions, such as whether to use an isolated or non-isolated driver, and the maximum propagation delay acceptable in the application. Decades of experience developing these circuits provide a wealth of expertise, literature, and best practices to draw upon.

But the design guidelines that apply to silicon transistors cannot be directly applied to gate drive circuits for the new generation of wide bandgap (WBG) semiconductors: silicon carbide (SiC) MOSFETs and gallium nitride (GaN) high electron mobility transistors (HEMTs).

This article draws on Future Electronics’ experience in developing the GaNdalf reference design board and TobogGaN ultra-compact 60 W AC-DC converter for bridgeless totem-pole power factor correction (PFC) systems to provide discrete gate selection for WBG semiconductors Solutions to potential pitfalls when driving.

Key Parameters Affecting Gate Driver Performance

Designers typically study a handful of key parameters specified in the data sheet to measure the performance of a discrete gate driver. These parameters include:

• Negative Input/Output Voltage Handling: This shows how sensitive the circuit is to ground plane bounce noise in the presence of parasitic capacitance and inductance created by non-ideal board layout.
• Propagation delay: The shorter the delay, the faster the response to the control signal. This can severely impact performance in high frequency switching applications. For example, an excessively long propagation delay can disrupt the timing of the primary-side driver and the secondary-side synchronous rectifier driver.
・ Delay Matching: In dual-channel gate drivers used to drive multiple parallel switches, better delay matching helps improve circuit robustness and reliability.
• Operating temperature range: The higher maximum operating temperature allows it to withstand higher power consumption at higher ambient temperatures.

Figure 1 shows typical values ​​of these parameters for silicon power switches (MOSFETs and IGBTs) and WBG semiconductors. It is clear that there are some substantial differences in key parameters between silicon and WBG devices, even SiC MOSFETs and GaN HEMTs. SiC MOSFETs and GaN HEMTs can operate at frequencies ten times higher than standard silicon devices and can withstand higher temperatures while producing lower switching and conduction losses. These features are very attractive to designers of applications such as EV chargers, USB Type-C® power adapters, solar inverters, etc.: In all of these applications, the use of WBG switches enables the development of smaller, lighter, more efficient power circuit.

Lessons learned from real-world applications: How to drive the gates of wide-bandgap semiconductor devices
Figure 1: Typical specifications for various types of power switches (Image source: Future Electronics)

Design Requirements for WBG Drivers

The large differences in silicon and WBG switches mean that WBG devices require dedicated gate drivers. The growing demand for WBG devices is prompting WBG device manufacturers to invest more in gate drivers to complement their switching products. Greater availability and product choices make the market more competitive, reducing the premium on these specialized devices.

So what issues determine how to choose the right gate driver for a SiC MOSFET or GaN HEMT?

The first question to consider is which topology the device is used for. For soft switching topologies such as LLC circuits in DC-DC power stages, isolated drivers are not necessarily required and more economical non-isolated drivers can be used.

For hard-switching topologies, such as the bridgeless totem-pole PFC system in the GaNdalf reference design, the situation is different. An isolated gate driver is recommended here, at least in high-side switches.

For half-bridge topologies, half-bridge (dual) gate drivers save space by integrating the high-side and low-side drivers of the bridge in one package. However, sometimes two single-channel drivers provide designers with more flexibility. In applications with switching frequencies above 150 kHz, using two drivers can help reduce common-mode noise.

The choice of GaN HEMT driver depends on which of two types it is: the cascaded type is easier to drive because it has an integrated low-voltage silicon FET. The gate driver drives this FET, not the GaN device itself, so a standard, economical gate driver for silicon devices is a suitable choice. The downside is that this low voltage FET increases the output capacitance, which limits the switching speed (dv/dt), resulting in higher switching losses.

Another type is the enhancement-mode (e-type) GaN HEMT. It requires a dedicated GaN gate driver, detailed below.

Gate Drivers for SiC MOSFETs

One of the reasons design engineers end up choosing a dedicated gate driver for a SiC MOSFET is that each MOSFET manufacturer recommends a different gate-to-source voltage to drive their product. Some manufacturers will advise users to drive their SiC MOSFETs with negative voltages. This ensures complete device turn-off and eliminates the risk of spurious turn-on in devices with low gate-to-source voltage thresholds. For others, a negative voltage is not needed to turn off the device because they have a higher gate-to-source voltage threshold.

When evaluating drivers, the data sheet can explain how SiC MOSFETs work. The main parameters of the study were:

・Transmission characteristics at different temperatures Id = f(Vgs)
・ Output characteristics at different gate-source voltage Vgs Id = f(Vds)
・Drain-source on-resistance at different Vgs Rds(on) = f(Id)

In fact, the gate-source voltage has a big effect on the on-resistance: according to the data sheet, sometimes SiC MOSFETs with lower on-resistance end up with higher conduction losses simply because the recommended gate-source voltage is not used.

Switching losses are also strongly influenced by the power system design. Capacitive turn-on is a common cause of high switching losses in SiC MOSFETs. If the sensed gate-to-source voltage related to the device capacitance ratio is higher than the nominal threshold voltage, there is a higher risk of the capacitance turning on, as shown in Figure 2. When the threshold voltage is higher than the sensed gate-source voltage, designers should seek a positive balance to protect the device from parasitic turn-on.

Lessons learned from real-world applications: How to drive the gates of wide-bandgap semiconductor devices
Figure 2: Capacitive turn-on effect in SiC MOSFETs (Image credit: Infineon)

Another concern when choosing a gate driver for fast switching SiC MOSFETs is noise. An important parameter to consider is the gate-drain capacitance Cgd. When high gate-drain capacitance is combined with low threshold voltage, MOSFETs can be susceptible to Miller turn-on effects. In addition, voltage coupling due to the inherent capacitance of the device can lead to poor switching waveforms and undesirable cross-conduction effects.

There’s a remedy: Future Electronics’ recommendation is to look at the SiC MOSFET’s data sheet for the gate-drain capacitance ratings, and the ratio of gate-source capacitance to gate-drain capacitance. If the gate-to-drain capacitance is relatively high, it may be necessary to choose a gate driver with Miller clamping. In the case where the ratio of gate-source capacitance and gate-drain capacitance is low, it is better to use an external capacitor to increase the gate-source capacitance.

An evaluation conducted by the Future Electronics Engineering Center of Excellence using the GaNdalf development platform shows that the driver with Miller clamping combined with the additional gate-source capacitance improves switching performance and overall system operation, significantly increasing efficiency and improving switching waveform, reducing total harmonic distortion.

Experience has shown that the best performance is achieved with dedicated SiC gate drivers. However, simpler and more economical gate drivers can be chosen: in this case, the designer must implement external circuitry to regulate the operation of the SiC MOSFET, or the system may experience severe thermal problems, resulting in reduced efficiency and EMI Increase.

Gate Drivers for Enhancement Mode GaN HEMTs

Enhancement-mode GaN HEMTs, such as Infineon’s CoolGaN™ family, have low threshold voltages, typically 1.2 V, and peak gate drive currents typically less than 1 A at 8 V drive voltage. A steady state current of 5 mA to 10 mA is required to keep the device on.

A negative gate-to-source voltage turns off the HEMT, sinking current peaks from the gate. The voltage then returns to 0 V and back to negative after a longer interval to maintain the off state, as shown in Figure 3.

Lessons learned from real-world applications: How to drive the gates of wide-bandgap semiconductor devices
Figure 3: Voltage and current waveforms of a GaN HEMT during a switching cycle (Image source: Infineon)

It is important to choose a driver that can configure the timing of these operations: this avoids the risk of damaging the HEMT, as a single overshoot on the gate-source voltage could permanently damage the device.

Advantages of integrated drives and HEMTs

In most low-power applications, i.e. less than 1 kW, the driver is usually integrated with a GaN HEMT. A single package simplifies board layout and reduces leakage of EMI from high frequency switching to the rest of the system.

Examples of such integrated devices are Power Integrations’ InnoSwitch™3 and InnoSwitch4-CZ for applications up to 100 W. The devices integrate a PowiGaN HEMT rated up to 750 V, a quasi-resonant power controller, a FluxLink™ interface without optocouplers, and a synchronous rectification controller.

Designers can use these devices to achieve very high power densities: Future Electronics’ TobogGaN board is a 60 W AC-DC power supply measuring 58 mm x 49 mm x 32 mm with a power density of 20 W/in3. At the heart of this board is Power Integrations’ InnoSwitch3-Pro.

Another option is ST’s MasterGaN® platform for soft-switching topologies up to 500 W.

In addition, Infineon’s CoolGaN Integrated Power Stages (IPS) pair CoolGaN 600 V enhancement-mode GaN switches with dedicated EiceDRIVER™ gate drivers in thermally enhanced QFN packages. This IPS device is available in single-channel and half-bridge configurations.

Proven technology for matching drivers and switches

This article shows that extra care is needed when choosing gate drivers for SiC MOSFETs or GaN HEMTs, but that WBG semiconductor-based power systems can deliver higher performance and reliability at a lower cost than silicon if implemented properly.

While gate drivers for SiC MOSFETs require careful review of data sheet values ​​and the risk of parasitic turn-on events, users of GaN HEMTs can choose from a variety of integrated driver/switch packages that are in the middle of An off-the-shelf solution is provided when selecting the right driver for low power applications.

development board

Development board name: Gaandalf II
Development board manufacturer: Future Electronics
Description: The GaNdalf II board provides an adaptable and flexible solution for designing bridgeless power factor correction circuits based on Infineon’s latest CoolGaN enhancement mode power transistors. Offering peak efficiency above 99% and total harmonic distortion below 5%, the GaNdalf II is an ideal starting point for efficient power conversion designs driving loads up to 2 kW.

Development board name: TobogGaN
Development board manufacturer: Future Electronics
Description: The 60 W TobogGaN reference design board is a complete AC-DC converter for industrial and communications auxiliary power supplies. It is also suitable for any general purpose application requiring high efficiency, small size or the flexibility to use a single design in multiple end products.
At the heart of the development board is Power Integrations’ InnoSwitch™3-Pro, a highly integrated flyback controller that reduces component count and saves board space.

Appendix: Glossary of Terms

Threshold Voltage: The lowest voltage at which the gate capacitance charges to the point where the device just turns on.

Common-Mode Transient Immunity (CMTI): A key specification for isolated gate drivers, it is the maximum tolerable rate of rise or fall of a common-mode voltage applied between two isolated circuits. Usually measured in kV/μs or V/ns. A high CMTI means that the two isolation circuits on the transmitter side and the receiver side will function properly within the data sheet specifications.

Negative gate drive voltage: Generally not needed for high voltage MOSFETs, sometimes used for IGBTs. It is definitely required for most SiC and GaN switches.

Miller Clamp: A low impedance switch that redirects the current induced by dv/dt. Miller clamp keeps the device off by connecting the gate of the MOSFET to ground or to the negative voltage rail.

DESAT: The most common overcurrent protection circuit. It is the default choice for many applications because of its ease of implementation.

Bootstrap Circuit: A boost charge pump consisting of switches, capacitors, and diodes that uses a voltage equal to the sum of the switch voltage (Vin) and the internal supply voltage as the gate drive for the high-side N-channel MOSFET.

Dead Time: The period of time during which both devices are inactive to avoid any potential simultaneous turn-on in a half-bridge configuration. Several factors affect the deadtime setting: pulse width distortion, propagation delay, and rise and fall times. It is important to maintain minimum dead time to improve converter efficiency. During the dead time, current flows through the body diode. The voltage drop of the body diode is much larger than the device itself, so the conduction losses are also higher. The longer the dead time, the higher the losses, which reduce efficiency and generate heat. Therefore, it is best to minimize dead time by using gate drivers with low pulse width distortion, low propagation delay, and short rise and fall times.

Pulse Width Distortion: Determined by the mismatch in the propagation delays of the rising and falling edges.

Propagation delay: One of the key parameters of the gate driver, it affects the loss and safety of high frequency systems. It is defined as the time delay from a 50% change in the input to a 50% change in the output. This delay affects switching timing between devices, which is critical in high-frequency applications where dead time or off-time between devices is limited.

Under-Voltage Lockout (UVLO): Monitors the gate driver’s supply pin to ensure that the voltage remains above a certain threshold to maintain normal operation.

The Links:   CM800DU-12H LQ064V3DG04

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