The logic behind nearly all digital components today relies on two pairs of transistors – NMOS and PMOS. The same voltage signal turns on one of the transistors and turns the other off. Putting them together means that the current will only flow when there is a slight change, which greatly reduces power consumption. These pairs of transistors have been next to each other for decades, but if circuits are to continue to shrink, they must be brought closer together.

Intel (Intel) demonstrated a completely different arrangement at this week’s IEEE International Electron Devices Meeting (IEDM): stacking one pair of transistors on top of another. This scheme effectively halves the area occupied by a simple CMOS circuit, which means that the TRANSISTOR density on an IC chip may be doubled in the future.

The scheme first uses the widely recognized next-generation transistor structure, which is known by various names, including nanosheet (Nanosheet), nanoribbon (Nanoibbon), nanowire (Nanowire) or gate-all-around structure (Gate-All-Around, GAA) element. In contrast to the current common practice where the majority of transistors are composed of vertical silicon fins, the channel region of Intel nanosheets is composed of multiple horizontal nanoscale sheets stacked on top of each other.

　With self-aligned process recipes, modifying the manufacturing steps becomes the focus of the process

Intel engineers use these components to create minimalist CMOS logic circuits, known as inverters. It requires two transistors, two power supply wires, one input wire and one output wire. Even the transistors are placed side-by-side like they are currently, but very tightly packed. By stacking transistors and adjusting the interconnects, the inverter area is halved.

Intel’s recipe for creating stacked nanosheets is called a “Self-Aligned” process because it essentially builds two devices in the same steps. This is important because adding a second step (eg, building them on separate wafers and then bonding the wafers together) can lead to misalignment of the wafers, which in turn can cause damage to any potential circuitry.

The core focus of the process is to modify the fabrication steps of nanosheet transistors. It starts with repeating layers of silicon and silicon germanium. It was then etched into a tall, narrow fin before the silicon germanium was etched away, leaving a set of suspended silicon nanosheets. Typically, all nanosheets form a single transistor. But here, the top two nanosheets are connected to Phosphorous-Doped Silicon for the purpose of forming an NMOS device, while the bottom two nanosheets are connected to boron-doped silicon germanium. germanium) to generate PMOS.

　　Simplify the integration process and introduce strain into your own components

This whole “integration process” is of course much more complicated, but Intel researchers have been working hard to make it as simple as possible, said Robert Chau, Intel senior fellow and director of component research. “The integration process can’t be too complicated, as this will affect the feasibility of making chips in stacked CMOS. It turned out to be a very practical process with impressive results.”

“Once you get the hang of it, the next step is to start pursuing performance,” he said. This could include improvements to PMOS components, which currently lag NMOS in drive current. Chau further pointed out that the answer to this question may be to introduce “strain” in the transistor channel. The idea is to distort the silicon crystal lattice by rapidly passing through charge carriers (holes in this case). Intel introduced strain into its own components as early as 2002. In another study at the IEDM conference, Intel demonstrated a method to simultaneously generate compressive strain (Compressive Strain) and tensile strain (Tensile Strain) in nanoribbon transistors.

Other research groups are also working on the design of stacked nanosheets, although they are sometimes referred to as complementary field-effect transistors (CFETs). The Belgian research organization Imec pioneered the concept of CFETs and published a research report on the implementation of CFETs at the IEEE Symposium on Very Large Integrated Circuits (VLSI Symposia) last June. However, Imec devices are not entirely made of nanosheet transistors. Instead, the bottom layer consists of fin field-effect transistors (FinFETs), and the top layer is a single nanosheet. Taiwanese researchers have published a study on the implementation of CFETs, with one nanosheet each for PMOS and NMOS on the structure. In contrast, Intel’s circuit has a 2nm nanosheet NMOS on top of a 3nm nanosheet PMOS, which is closer to what a device should look like when stacking is necessary.