“The data clock input (DCI) frequency of the AD9139 can be as high as 575 MHz. Since data captured on both rising and falling edges is fed into a single DAC, data rates in 1× mode can be as high as 1150 MSPS. To support quadrature data, two AD9139 devices are used to generate baseband data. The analog output of each channel goes into its own low-pass filter.

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Evaluation and Design Support

Circuit Evaluation Board
AD9139/ADL5375 Evaluation Board (AD9139-DUAL-EBZ)
Digital Pattern Generator Evaluation Board (AD-DPG3)
Design and integration files
Schematics, layout files, bill of materials, software

Circuit functions and advantages

The circuit shown in Figure 1 provides a synchronous wideband transmitter that supports ultra-wide I/Q bandwidths up to 1150 MHz. The design demonstrates high in-band signal performance, such as high spurious-free dynamic range (SFDR), low error vector magnitude (EVM), and flat frequency response over a wide frequency range.

Synchronization performance between multiple channels is especially important for quadrant error correction (QEC). When multi-chip synchronization is enabled, the delay mismatch between converters can be within one clock cycle and there is a well-aligned synchronization clock.

The challenge of high-speed synchronization is to achieve digital-to-analog (DAC) clock cycle accuracy in process, voltage, and temperature (PVT). Achieving this accuracy requires implementing synchronization logic blocks on the DAC, and careful layout and clocking schemes must be designed on the board to work with the synchronization logic blocks.

This circuit can be used to support wideband point-to-point applications in the E-band, which ensures both zero intermediate frequency (ZIF) and complex intermediate frequency (CIF). Excellent synchronization performance enables it to support stringent alignment requirements in applications such as radar.

Figure 1. AD9139-DUAL-EBZ Evaluation Board Functional Block Diagram

Figure 2. AD9139-DUAL-EBZ Evaluation Board Used to Implement the Circuit

circuit description

The board shown in Figure 2 uses dual AD9139 single-channel TxDACs, the ADL5375-05 wideband quadrature modulator, and the AD9516-1 clock generator.

The data clock input (DCI) frequency of the AD9139 can be as high as 575 MHz. Since data captured on both rising and falling edges is fed into a single DAC, data rates in 1× mode can be as high as 1150 MSPS. To support quadrature data, two AD9139 devices are used to generate baseband data. The analog output of each channel goes into its own low-pass filter. Therefore, the reference design can support composite bandwidths up to 1150 MHz, as shown in Figure 3. Flatness over such a large range is critical. Since the AD9139 includes an inverse sinc filter that cancels the effects of the DAC’s inherent sinc roll-off, post-DAC filter flatness becomes critical to overall flatness. A DDR clock frequency of 575 MHz is high for a parallel low-voltage differential signaling (LVDS) interface. The timing of the LVDS interface needs to be carefully designed.

Figure 3. Maximum Bandwidth of Dual AD9139 Devices

Quadrature Modulator

The ADL5375-05 is a wideband quadrature modulator with an output frequency range of 400 MHz to 6 GHz. The ADL5375-05 interfaces with the AD9139 as an I/Q modulator that has a wide frequency range of 400 MHz to 6 GHz. The output of the AD9139 and the input of the ADL5375-05 share the same common-mode level of 0.5 V.

Clock Generation and Considerations

Due to synchronization requirements, the DACCLK, synchronization clock, and frame clock must be well aligned for both AD9139 devices. The AD9516-1 supports the necessary clock distribution functions, as well as an integrated voltage-controlled oscillator (VCO) and phase-locked loop (PLL) for higher frequency generation. Better clock phase noise facilitates high-speed alignment when the VCO and PLL are disabled and the AD9516-1 is in clock distribution mode. When used as a clock distribution mode, the additive phase noise is 147 dBc/Hz at a 1 GHz output with a divide ratio of 1 and a 10 MHz offset. The Rohde & Schwartz SMA100A has excellent phase noise performance, and when used as an input to the AD9516-1, the AD9516-1 output total phase noise is close to the minimum limit of the AD9516-1 in clock distribution mode.

Multi-Chip Synchronization with AD9139

Synchronization between dual channels is critical for QEC. Layout symmetry is required between the DACCLK and the sync clock. Additionally, the phase between DACCLK and the sync clock must not fall within the setup and hold time window (also known as hold out of window (KOW)).

The synchronization mechanism can achieve that the mismatch in PVT between multiple channels on the DAC output is less than one DAC clock cycle. The following are guidelines for achieving test performance:

1. DACCLK 1 and DACCLK 2 must be well aligned on the pins of the AD9139. The mismatch between DACCLK 1 and DACCLK 2 will add to the final mismatch on the output.
2. Sync Clock 1 and Sync Clock 2 must be well aligned and sampled by DACCLK1 and DACCLK2, respectively, for reference.
3. The relative phase between the DACCLK and the sync clock must not fall within the KOW as shown in Figure 4.

Figure 4. Timing Requirements Between DACCLK and Synchronous Clock

LVDS interface design

At DCI = 575 MHz, designing an LVDS interface in a PVT is often a challenge. This section uses an example to illustrate how to design and optimize this interface.

Taking Figure 5 as an example, DCI = 491 MHz. According to the AD9139 data sheet specification, if the edges of DCI and DATA are well aligned on the pins of the AD9139, the KOW (setup time + hold time) can be placed in the middle of the valid window when the delay-locked loop (DLL) phase is set to zero.

The data valid margin is defined by the following formula.

T_{DATA VALID MARGIN} = T_{DATA PERIOD} − T_{DATA SKEW} − T_{DATA JITTER} − (T_HOLD + T_SETUP)

Over process variation, voltage and temperature, T_{DATA VALID MARGIN}Must be > 0 to ensure proper sampling of data.

When DCI = 491 MHz (see Figure 5),
At DCI = 491 MHz (see Figure 5),
• T_{DATA PERIOD} = 1018ps
• T_HOLD + T_SETUP = 517ps
• T_{DATA SKEW} + T_{DATA JITTER}Must be less than 501 ps in PVT, which is a user-implemented requirement. T_{DATA SKEW}Including LVDS data bus delay mismatch, skew between DCI and DATA bus in PVT, etc.

To optimize the interface design, the user can do the following:

• Use the shortest possible traces of the same length on the printed circuit board (PCB).
• Optimize Field Programmable Gate Arrays (PFGAs) by ensuring:
• The edges of DCI and DATA are well aligned on the pins of the AD9139.
• The less drift between DCI and DATA the better over temperature and voltage changes.
• The less jitter between DCI and DATA, the better.

After scanning the DLL phase, the AD9139’s sample error detection (SED) function can also be used to check the timing relationship between DCI and DATA.

Figure 5. LVDS Timing Requirements

Low Pass Filter Design

For experimental purposes, in order to make the performance of the AD9139 not limited by the filter, a filter with good flatness and group delay performance within 240MHz was designed on the board. In actual product development, out-of-band rejection can be enhanced by increasing the filter order.

The filter topology shown in Figure 6 is a fifth-order Butterworth filter with a corner frequency of 900 MHz. The simulated response curve of this filter is shown in Figure 7. The simulated flatness is ±0.1 dB (DC to 240 MHz). The simulated group delay curve for this filter is shown in Figure 7.

Figure 6. Recommended DAC Modulator Interface Topology (F_C = 900 MHz, fifth-order Butterworth filter)

Figure 7. Frequency response of a DAC modulator interfaced with a 900 MHz fifth-order Butterworth filter (simulated)

Figure 8. Group Delay of Filters

Layout suggestion

Special attention should be paid to the layout of the AD9139 and ADL5375 interfaces. Here are some suggestions for getting better noise and spurious performance. Figure 9 shows a top-level layout diagram that follows these recommendations:

• Place the DAC, filter and modulator on the same side of the PCB.
• Tighten filter placement: reduce the L and C forbidden area margins.
• Connect the ground capacitor to the GND plane in three ways.
• Shorten the distance from the DAC to the modulator.
• Keep all I/Q differential trace lengths well matched.
• Place filter termination resistors as close as possible to the modulator inputs.
• Place the DAC output 50 Ω resistor as close to the DAC as possible.
• L and C use 0402 packages.
• Widen the traces through the filter network to reduce signal loss.
• Place vias around all DAC output traces, filter networks, modulator output traces, and LO input traces.
• Route the local oscillator (LO) and modulator output traces on different layers or at a 90° angle to each other to prevent coupling.

Figure 9. General layout recommendations

Visit www.analog.com/CN0432-DesignSupport for a design support package and learn more about proper layout in the accompanying AD9139-DUAL-EBZ layout file.

Circuit Evaluation and Testing

The following section describes how to set up and test the evaluation board. These steps outline the basic steps required to implement the evaluation board functionality and results. For more detailed information, see the AD9139-DUAL-EBZ Evaluation Board Quick Start Guide.

required equipment

The following hardware is required:
• AD9139-DUAL-EBZ
• AD-DPG3
• Agilent E3631A power supply (or equivalent)
• Spectrum Analyzer PXA N9030A
• Rohde & Schwartz SMA100A Signal Generator
• PC with USB port
• USB cable

The following software is required:

• DPG downloader
• ACE software

Test setup

The following sections describe the details of measuring adjacent channel power (ACP) and modulation error ratio (MER) performance using 64 QAM digital modulation. The test setup is flexible and other measurements can be performed. The test setup is shown in Figure 10 below. The hardware, SPI software, Quick Start Guide (QSG), and DPG3 hardware and software for the AD9139-DUAL-EBZ evaluation board are released.

Use a Keysight E3631 to supply 5 V to the board on P5/P6. An R&S SMA100A is used to provide the input clock to the AD9516-1 on the board. An additional R&S SMA100A is used to provide the LO clock to the ADL5375-05. The AD9139 is programmed through serial peripheral interface (SPI) software. The DPGDownloader running on the PC generates the AD9139’s launch vector and downloads it to the DPG3. The output of the ADL5375-05 is fed into the Keysight PXA N9030A.

Figure 10. Test setup functional block diagram

Measurement results

Figure 11. ACP measurement, LO = 2.5 G, BW = 6 × 80 = 480 MHz (CIF)

Figure 12. MER/EVM measurement, LO = 2.5 G, BW = 6 × 80 = 480 MHz (CIF)